1. Field of the Invention
The present invention relates to a memory device having a non-volatile memory, a memory management method, and a program which can be applied to, for example, a NAND flash memory.
2. Description of the Related Art
A NAND flash memory allows data to be operated electrically, by “writing”, “reading” and “erasing”.
For example, since rewriting of bits by “writing” is performed in only one direction from “1” to “0”, to write data anew, it is necessary to perform “writing” after setting all bits to “1” once by “erasing”.
As shown in FIG. 1, in a NAND flash memory, the minimum unit of writing/reading is a page PG, and the minimum unit of “erasing” is a block BLK as a collection of a plurality of pages.
For example, a page PG includes 512 bytes plus spare 16 bytes, thus 528 bytes or 4224 bits. A block BLK includes 32 pages of PG0 to PG31.
Since the minimum unit of “writing” is several tens of times larger than the minimum unit of “erasing”, it is necessary to devise some measure to perform rewriting of a NAND flash in an efficient manner.
As shown in FIG. 2, each page PG of a NAND flash memory is made up of a data area 1 into which data is written, and a spare area 2 into which additional information is written.
Generally, in a NAND flash memory, it is necessary to perform writing to pages PG within a block BLK (including the spare area) in order from the lowest-numbered page as shown in FIG. 3A. That is, in a NAND flash memory, random writing within a block BLK is prohibited.
Also, in a NAND flash memory, unusable blocks called defect blocks exist at the time of shipment, and it is necessary to perform reading/writing from/to the NAND flash memory while avoiding these defect blocks.
A NAND flash memory has the above-mentioned features. In this regard, it is desirable to allow existing file systems and tools to be used as they are, or only after slight modifications, with respect to the NAND flash memory as well.
To this end, it is necessary to allow a NAND flash memory to be used without concern for “erasing” operations or defect blocks.
Accordingly, it is necessary to install a layer for interpreting a request from the using side of the NAND flash memory, for example, a file system, and translating the request into a command for operating the NAND flash memory (logical-physical translation layer).
Various related techniques have been proposed in this regard (see, for example, Japanese Unexamined Patent Application Publication No. 2003-36209 and Japanese Unexamined Patent Application Publication No. 2002-32256).
The non-volatile memory described in Japanese Unexamined Patent Application Publication No. 2003-36209 includes a mechanism for returning to the normal storage state even in the event of a system down during device operation such as a power outage. Also, the unit of logical address-physical address translation (logical-physical translation) in this non-volatile memory is a block size, and the write size is a block size.
Also, in the NAND flash memory described in Japanese Unexamined Patent Application Publication No. 2002-32256, logical-physical translation is done in page units, which allows for more efficient rewriting of data than logical-physical translation in block units.